The present invention relates to semiconductor devices and manufacturing methods thereof, and more specifically, to a technique that can be suitably applied to a semiconductor device including a MISFET that operates at high voltage of, e.g. several tens of V, and a manufacturing method thereof.
Semiconductor devices are configured by forming a number of circuit elements, including a MOSFET, a resistor, and a capacitor, over a main surface of a semiconductor substrate formed of a monocrystalline silicon etc., and coupling the respective circuit elements so as to perform a required circuit operation and function.
In recent years, semiconductor devices have pursued the miniaturization of elements or the use of multiple power sources (increase of a voltage etc.) to meet the demands from market. However, together with the miniaturization of the elements, there arises a problem that the life of a gate oxide film in a MOS transistor is reduced due to hot carriers. This is mainly caused by impact ionization due to an electric field concentration at an end of a drain region.
For this reason, in the related art, some semiconductor devices employ a lightly doped drain (LDD) structure that includes a drain region comprised of a region with a low impurity concentration (low-concentration region) and another region with a high impurity concentration (high-concentration impurity region), thereby relieving the electric field concentration at the end of the drain region.
For example, Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2000-100964) discloses a technique for a semiconductor device having a plurality of types of MOS transistors with different voltages applied. In the technique, a sidewall spacer length (length of a sidewall insulating film) is adjusted by changing the thickness of a gate electrode for each type of the MOS transistor, so that an offset length (distance from the end of the gate electrode to a high-concentration region) of the MOS transistor, which is intended to reduce hot carriers most, is set longer than that of each of other MOS transistors.